1. Field of the Invention
This invention relates to a semiconductor device of the type employing a trench gate structure and also to fabrication methodology thereof.
2. Description of Related Art
As power devices capable of realizing low on-resistances and high-speed switching performances, trench gate type metal oxide semiconductor (MOS) transistors and insulated gate bipolar transistors (IGBTs) are known. FIG. 14 shows an example of the trench-gate MOS transistors (JP-A-2000-183337). This MOS transistor has an n+-type source layer and its underlying p-type base layer, with a stripe-shaped (or mesh-like) trench formed to vertically extend from the n+-source and penetrate the p-base layer resulting in subdivision into a plurality of regions. Each divided region becomes a unit cell with a gate electrode formed at the base layer which is exposed to trench side surfaces. More specifically, each unit cell makes up a vertical MOS transistor with an n+-type drain layer commonly used or xe2x80x9csharedxe2x80x9d by adjacent ones of vertical transistors.
The trench-buried gate electrode is generally made of olycrystalline silicon or xe2x80x9cpolysiliconxe2x80x9d doped with a chosen impurity. However, such polysilicon gate is limited in electrical resistivity reduction even when phosphorus or arsenic is heavily doped thereinto at an increased concentration. In order to realize ultra-high speed switching operations, a need is felt to further lower the electrical resistance of the gate electrode per se. To this end, with the device of FIG. 14, a silicide film is formed on the surface of the buried polysilicon gate for achievement of the low gate-electrode resistivity required.
The silicide film for reduction of the polysilicon gate resistance is typically fabricated by forming on the surface of a polysilicon film a conductive film made of a metal such as titanium (Ti), cobalt (Co), nickel (Ni) or the like and then thermally processing it to permit the metal film to react with the polysilicon. Unfortunately, this silicide process is encountered with a problem that the sheet resistance unacceptably increases when on-chip gate wiring leads are narrowed beyond a predetermined degree. It has been found that in case the gate width is decreased to less than 1 micrometer (xcexcm), a Ti silicide (TiSi2) film formed on a phosphorus-doped polysilicon gate results in a critical increase in the sheet resistance. This is called the xe2x80x9cthin linexe2x80x9d effect (see xe2x80x9cRevolution of Logic LSI Technologiesxe2x80x9d, published by Science Forum Corporation), also known as xe2x80x9cedge thinningxe2x80x9d effect or simply xe2x80x9cedgexe2x80x9d effect.
In the trench-gate semiconductor device shown in FIG. 14 also, this thin-line effect pauses serious problems if the trench gates further shrink in dimension in pursuance of the quest for higher chip integration in the near future. This would result in reduction or loss of the effectiveness of the silicide process. As far as the trench gate width is designed to stay at 1 xcexcm or greater, the thin-line effect is avoidable. However, in view of the fact that the trench gate is effective only at their side surfaces opposing the base layer enlarging the trench width would result in unwanted increases in gate capacity and in gate area. This in turn leads to a decrease in switching performance and also to an increase in on-state resistance, which occurs due to a relative decrease in source area within the chip.
Accordingly in the trench-gate semiconductor devices, it is desired to perform shrinkage or miniaturization of a trench gate without having to reduce or loose the inherent effectiveness of the silicide process.
A trench gate type semiconductor device includes a first semiconductor layer having first and second main surfaces, a second semiconductor layer of a first conductivity type as formed on the first main surface of the first semiconductor layer, a third semiconductor layer of a second conductivity type as formed on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type as formed at a surface of the third semiconductor layer, a gate electrode having a polycrystalline silicon layer being buried in a trench formed to a depth reaching the second semiconductor layer from a surface of the fourth semiconductor layer with a gate insulating film interposed therebetween and having an upper end portion protruding upwardly from a trench upper end opening while having its width greater than a width of the trench and a metal silicide film formed at an upper surface and side surfaces of the upper end portion of the polycrystalline silicon layer, a first main electrode in contact with both the fourth semiconductor layer and the third semiconductor layer, and a second main electrode formed at the second main surface of the first semiconductor layer.
A method of fabricating a trench gate type semiconductor device includes: forming a second semiconductor layer of a first conductivity type on a first main surface of a first semiconductor layer having first and second main surfaces, doping an impurity into a surface of the second semiconductor layer to thereby form a third semiconductor layer of a second conductivity type, doping an impurity into a surface of the third semiconductor layer to form a fourth semiconductor layer of the first conductivity type, forming a trench extending from a surface of the fourth semiconductor layer and penetrating the third semiconductor layer to have a depth reaching the second semiconductor layer, after having formed a gate insulating film on inner surfaces of the trench, depositing over the fourth semiconductor layer a polycrystalline silicon layer in such a manner as to completely bury the trench, etching the polycrystalline silicon layer to form a gate electrode having its main part buried in the trench and an upper end portion protruding upwardly from a trench upper end opening while having a width greater than a width of the trench, forming a metal silicide film at an upper surface and side surfaces of the upper end portion of the gate electrode, and forming a first main electrode in contact with both the fourth semiconductor layer and the third semiconductor layer and a second main electrode in contact with the second main surface of the first semiconductor layer, respectively.